Altera cyclone V Technical Reference page 2303

Hard processor system
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cv_5v4
2016.10.28
hcint5 Fields
Bit
13
desc_lst_rollintr
12
xcs_xact_err
11
bnaintr
10
datatglerr
USB 2.0 OTG Controller
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Name
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
This bit is valid only when Scatter/Gather DMA mode
is enabled. The core sets this bit when the
corresponding channel's descriptor list rolls over. for
non Scatter/Gather DMA mode, this bit is reserved.
Value
0x0
0x1
This bit is valid only when Scatter/Gather DMA mode
is enabled. The core sets this bit when 3 consecutive
transaction errors occurred on the USB bus. XCS_
XACT_ERR will not be generated for Isochronous
channels.for non Scatter/Gather DMA mode, this bit
is reserved.
Value
0x0
0x1
This bit is valid only when Scatter/Gather DMA mode
is enabled. The core generates this interrupt when the
descriptor accessed is not ready for the Core to
process. BNA will not be generated for Isochronous
channels. for non Scatter/Gather DMA mode, this bit
is reserved.
Value
0x0
0x1
This bit can be set only by the core and the applica‐
tion should write 1 to clear it. In Scatter/Gather DMA
mode, the interrupt due to this bit is masked in the
core.
Value
0x0
0x1
Description
Description
No Descriptor rollover interrupt
Descriptor rollover interrupt
Description
No Excessive Transaction Error
Excessive Transaction Error
Description
No BNA Interrupt
BNA Interrupt
Description
No Data Toggle Error
Data Toggle Error
18-213
hcint5
Access
Reset
RO
0x0
RO
0x0
RO
0x0
RO
0x0
Altera Corporation

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