Altera cyclone V Technical Reference page 2476

Hard processor system

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This register indicates the status of the core with respect to USB-related events. It must be read on

interrupts from Device All Interrupts (DAINT) register.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

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When the application sets this bit, the core initiates

remote signaling to wake up the USB host. The

application must Set this bit to instruct the core to

exit the Suspend state. As specified in the USB 2.0

specification, the application must clear this bit 115

ms after setting it. Remote Wakeup Signaling

(RmtWkUpSig) When LPM is enabled, In L1 state the

behavior of this bit is as follows: When the application

sets this bit, the core initiates L1 remote signaling to

wake up the USB host. The application must set this

bit to instruct the core to exit the Sleep state. As

specified in the LPM specification, the hardware will

automatically clear this bit after a time of 50us

(TL1DevDrvResume) after set by application.

Application should not set this bit when GLPMCFG

bRemoteWake from the previous LPM transaction

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

No exit suspend state

Exit Suspend State

Base Address

USB 2.0 OTG Controller

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