Altera cyclone V Technical Reference page 2152

18-62
gintsts
The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to
avoid any interrupts generated prior to initialization.
Module Instance
usb0
usb1
Offset:
0x14
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
wkupint sessr disco
eqint nnint
RO 0x0
RO
0x0
15 14
Reserved isoou enumd
tdrop
RO
0x0
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
ConID Reser ptxfe
StsCh ved mp
ng
RO RO
0x0 RO 0x1
0x1
13 12 11 10
usbrs usbsu erlys
one t sp usp
RO RO RO RO
0x0 0x0 0x0 0x0
Base Address
0xFFB00000
0xFFB40000
Bit Fields
25 24 23 22
hchin prtin reset fetsu
t t det sp
RO RO RO RO
0x0 0x0 0x0 0x0
9 8 7 6
Reserved goutn ginna
akeff keff
RO RO
0x0 0x0
Register Address
0xFFB00014
0xFFB40014
21 20 19 18
incom incom oepin iepin
plp pisoi t t
n
RO RO RO
0x0 RO 0x0 0x0
0x0
5 4 3 2
Reser rxflv sof otgin
ved l t
RO
RO 0x0 RO
0x0 0x0
USB 2.0 OTG Controller
cv_5v4
2016.10.28
17 16
epmis Reserved
RO
0x0
1 0
modem curmod
is
RO 0x0
RO
0x0
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