Altera cyclone V Technical Reference page 2229

Hard processor system
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cv_5v4
2016.10.28
hcchar0 Fields
Bit
Name
31
chena
30
chdis
28:22
devaddr
21:20
ec
USB 2.0 OTG Controller
Send Feedback
Description
When Scatter/Gather mode is disabled. This field is set
by the application and cleared by the OTG host.
Value
0x0
Indicates that the descriptor structure is not yet
ready
0x1
Indicates that the descriptor structure and data
buffer with data is setup and this channel can
access the descriptor
The application sets this bit to stop transmitting/
receiving data on a channel, even before the transfer for
that channel is complete. The application must wait for
the Channel Disabled interrupt before treating the
channel as disabled.
Value
0x0
No activity
0x1
Stop transmitting/receiving data
This field selects the specific device serving as the data
source or sink.
When the Split Enable bit of the Host Channel-n Split
Control register (HCSPLTn.SpltEna) is reset (0), this
field indicates to the host the number of transactions
that must be executed per microframe for this periodic
endpoint. for non periodic transfers, this field is used
only in DMA mode, and specifies the number packets
to be fetched for this channel before the internal DMA
engine changes arbitration. When HCSPLTn.SpltEna is
Set (1'b1), this field indicates the number of immediate
retries to be performed for a periodic split transactions
on transaction errors. This field must be Set to at least
2'b01.
Value
0x0
Reserved This field yields undefined results
0x1
1 transaction
0x2
2 transactions to be issued for this endpoint per
microframe
0x3
3 transactions to be issued for this endpoint per
microframe
Description
Description
Description
18-139
hcchar0
Access
Reset
RO
0x0
RO
0x0
RW
0x0
RW
0x0
Altera Corporation

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