Altera cyclone V Technical Reference page 2200

18-110
dieptxf12
Bit
15:0
inepntxfstaddr
dieptxf12
This register holds the size and memory start address of IN endpoint TxFIFOs implemented in Device
mode. Each FIFO holds the data for one IN endpoint. This register is repeated for each instantiated IN
endpoint FIFO. For IN endpoint FIFO 0 use GNPTXFSIZ register for programming the size and memory
start address.
Module Instance
usb0
usb1
Offset:
0x130
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
dieptxf12 Fields
Bit
29:16
inepntxfdep
15:0
inepntxfstaddr
dieptxf13
This register holds the size and memory start address of IN endpoint TxFIFOs implemented in Device
mode. Each FIFO holds the data for one IN endpoint. This register is repeated for each instantiated IN
Altera Corporation
Name
This field contains the memory start address for IN
endpoint Transmit FIFO 11.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This value is in terms of 32-bit words. Minimum value
is 16 Maximum value is 8192.
This field contains the memory start address for IN
endpoint Transmit FIFO 12.
Description
Base Address
0xFFB00000
0xFFB40000
Bit Fields
25 24 23 22
inepntxfdep
RW 0x2000
9 8 7 6
inepntxfstaddr
RW 0xA000
Description
Access
Register Address
0xFFB00130
0xFFB40130
21 20 19 18
5 4 3 2
Access
USB 2.0 OTG Controller
cv_5v4
2016.10.28
Reset
RW 0x8000
17 16
1 0
Reset
RW 0x2000
RW 0xA000
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