Altera cyclone V Technical Reference page 2469

cv_5v4
2016.10.28
Bit
23
descdma
13
endevoutnak
12:11
perfrint
10:4
devaddr
USB 2.0 OTG Controller
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Name
When the Scatter/Gather DMA option selected
during configuration of the RTL, the application can
Set this bit during initialization to enable the Scatter/
Gather DMA operation. This bit must be modified
only once after a reset.The following combinations are
available for programming:
GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave
mode GAHBCFG.DMAEn=0,DCFG.DescDMA=1
=> Invalid
GAHBCFG.DMAEn=1,DCFG.DescDMA=0 =>
Buffered DMA mode
GAHBCFG.DMAEn=1,DCFG.DescDMA=1 =>
Scatter/Gather DMA mode
Value
0x0
0x1
This bit enables setting NAK for Bulk OUT endpoints
after the transfer is completed for Device mode
Descriptor DMA It is one time programmable after
reset like any other DCFG register bits.
Value
0x0
0x1
Indicates the time within a (micro)frame at which the
application must be notified using the End Of
Periodic Frame Interrupt. This can be used to
determine If all the isochronous traffic for that
(micro)frame is complete. 0x0: 80% of the (micro)
frame interval 0x1: 85% 0x2: 90% 0x3: 95%
Value
0x0
0x1
0x2
0x3
The application must program this field after every
SetAddress control command.
Description
Description
Disable Scatter gather DMA
Enable Scatter gather DMA
Description
The core does not set NAK after Bulk OUT
transfer complete
The core sets NAK after Bulk OUT transfer
complete
Description
80% of the (micro)frame interval
85% of the (micro)frame interval
90% of the (micro)frame interval
95% of the (micro)frame interval
18-379
dcfg
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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