Altera cyclone V Technical Reference page 2505

Hard processor system
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cv_5v4
2016.10.28
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
Reserved
nyeti
nakin
ntrpt
trpt
RO
0x0
0x0
diepint0 Fields
Bit
14
nyetintrpt
13
nakintrpt
12
bbleerr
USB 2.0 OTG Controller
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software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
bblee
pktdr
Reser
rr
psts
ved
RO
RO
RO
0x0
0x0
Name
The core generates this interrupt when a NYET
response is transmitted for a non isochronous OUT
endpoint.
Value
0x0
0x1
The core generates this interrupt when a NAK is
transmitted or received by the device. In case of
isochronous IN endpoints the interrupt gets
generated when a zero length packet is transmitted
due to un-availability of data in the TXFifo.
0x0
0x1
The core generates this interrupt when babble is
received for the endpoint.
Value
0x0
0x1
Bit Fields
25
24
23
22
Reserved
9
8
7
6
bnain
txfif
txfem
inepn
tr
oundr
p
akeff
n
RO
RO
RO
0x0
RO
0x1
0x0
0x0
Description
Description
No interrupt
NYET Interrupt
Value
Description
No interrupt
NAK Interrupt
Description
No interrupt
BbleErr interrupt
diepint0
21
20
19
18
5
4
3
2
intkn
intkn
timeo
ahber
epmis
txfem
ut
r
p
RO
RO
RO
0x0
RO
0x0
0x0
0x0
Access
18-415
17
16
1
0
epdis
xfercomp
bld
l
RO
RO 0x0
0x0
Reset
RO
0x0
RO
0x0
RO
0x0
Altera Corporation

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