Altera cyclone V Technical Reference page 2141

Hard processor system
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cv_5v4
2016.10.28
Bit
7
nptxfemplvl
5
dmaen
4:1
hbstlen
USB 2.0 OTG Controller
Send Feedback
Name
Mode:Host and device. This bit is used only in Slave
mode. In host mode and with Shared FIFO with
device mode, this bit indicates when the Non-
Periodic TxFIFO Empty Interrupt bit in the Core
Interrupt register (GINTSTS.NPTxFEmp) is
triggered. With dedicated FIFO in device mode, this
bit indicates when IN endpoint Transmit FIFO empty
interrupt (DIEPINTn.TxFEmp) is triggered. Host
mode and with Shared FIFO with device mode:
Value
0x0
0x1
Mode:Host and device. Enables switching from DMA
mode to slave mode.
Value
0x0
0x1
Mode:Host and device. This field is used in Internal
DMA modes.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
Description
Description
DIEPINTn.TxFEmp interrupt indicates that
the IN Endpoint TxFIFO is half empty or
DIEPINTn.TxFEmp interrupt indicates that
the IN Endpoint TxFIFO is half empty
GINTSTS.NPTxFEmp interrupt indicates
that the Non-Periodic TxFIFO is completely
empty or DIEPINTn.TxFEmp interrupt
indicates that the IN Endpoint TxFIFO is
completely empty
Description
Core operates in Slave mode
Core operates in a DMA mode
Description
1 word or single
4 word or incr
8 word
16 word or incr4
32 word
64 word or incr8
128 word
256 word or incr16
Others reserved
18-51
gahbcfg
Access
Reset
RW
0x0
RW
0x0
RW
0x0
Altera Corporation

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