Altera cyclone V Technical Reference page 2205

cv_5v4
2016.10.28
hcintmsk1
This register reflects the mask for each channel status described in the previous section.
hctsiz1 on page 18-163
Buffer DMA Mode
hcdma1
on page 18-164
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
hcdmab1
on page 18-166
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcchar2
on page 18-166
Host Channel 2 Characteristics Register
hcsplt2 on page 18-169
Channel_number 2
hcint2
on page 18-171
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
hcintmsk2
This register reflects the mask for each channel status described in the previous section.
hctsiz2
on page 18-177
Buffer DMA Mode.
hcdma2 on page 18-178
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
hcdmab2
on page 18-180
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcchar3
on page 18-180
Channel_number: 3.
hcsplt3 on page 18-183
Channel_number 3
USB 2.0 OTG Controller
Send Feedback
on page 18-161
on page 18-175
Host Mode Registers Register Descriptions
18-115
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