Altera cyclone V Technical Reference page 2112

Hard processor system
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18-22
USB OTG Controller Module Registers Address Map
Register
hcintmsk5
on page 18-
216
hctsiz5
on page 18-
218
hcdma5
on page 18-219
hcdmab5
on page 18-
220
hcchar6
on page 18-
221
hcsplt6
on page 18-
224
hcint6
on page 18-226
hcintmsk6
on page 18-
230
hctsiz6
on page 18-
232
hcdma6
on page 18-233
hcdmab6
on page 18-
235
hcchar7
on page 18-
235
hcsplt7
on page 18-
238
hcint7
on page 18-240
hcintmsk7
on page 18-
244
hctsiz7
on page 18-
246
hcdma7
on page 18-247
hcdmab7
on page 18-
249
hcchar8
on page 18-
249
hcsplt8
on page 18-
252
hcint8
on page 18-254
Altera Corporation
Offset
Width Acces
s
0x5AC
32
RW
0x5B0
32
RW
0x5B4
32
RW
0x5B8
32
RW
0x5C0
32
RW
0x5C4
32
RW
0x5C8
32
RO
0x5CC
32
RW
0x5D0
32
RW
0x5D4
32
RW
0x5D8
32
RW
0x5E0
32
RW
0x5E4
32
RW
0x5E8
32
RO
0x5EC
32
RW
0x5F0
32
RW
0x5F4
32
RW
0x5F8
32
RW
0x600
32
RW
0x604
32
RW
0x608
32
RO
Reset Value
Host Channel 5 Interrupt Mask
0x0
Register
Host Channel 5 Transfer Size
0x0
Register
Host Channel 5 DMA Address
0x0
Register
Host Channel 5 DMA Buffer
0x0
Address Register
Host Channel 6 Characteristics
0x0
Register
Host Channel 6 Split Control
0x0
Register
Host Channel 6 Interrupt Register
0x0
Host Channel 6 Interrupt Mask
0x0
Register
Host Channel 6 Transfer Size
0x0
Register
Host Channel DMA Address
0x0
Registe
Host Channel 6 DMA Buffer
0x0
Address Register
Host Channel 7 Characteristics
0x0
Register
Host Channel 7 Split Control
0x0
Register
Host Channel 7 Interrupt Register
0x0
Host Channel 7 Interrupt Mask
0x0
Register
Host Channel 7 Transfer Size
0x0
Register
Host Channel 7 DMA Address
0x0
Register
Host Channel 7 DMA Buffer
0x0
Address Register
Host Channel 8 Characteristics
0x0
Register
Host Channel 8 Split Control
0x0
Register
Host Channel 8 Interrupt Register
0x0
cv_5v4
2016.10.28
Description
USB 2.0 OTG Controller
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