Altera cyclone V Technical Reference page 2292

Hard processor system
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18-202
hcintmsk4
31
30
15
14
Reserved
frm_
lst_
rolli
ntrms
hcintmsk4 Fields
Bit
13
frm_lst_rollintrmsk
11
bnaintrmsk
2
ahberrmsk
1
chhltdmsk
Altera Corporation
29
28
27
26
13
12
11
10
Reser
bnain
ved
trmsk
RW
0x0
k
RW
0x0
Name
This bit is valid only when Scatter/Gather DMA mode
is enabled.
0x0
0x1
This bit is valid only when Scatter/Gather DMA mode
is enabled.
0x0
0x1
In scatter/gather DMA mode for host, interrupts will
not be generated due to the corresponding bits set in
HCINTn.
0x0
0x1
Channel Halted.
0x0
0x1
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Reserved
Description
Value
Description
Mask
No mask
Value
Description
Mask
No mask
Value
Description
Mask
No mask
Value
Description
Mask
No mask
21
20
19
18
5
4
3
2
ahber
rmsk
RW
0x0
Access
USB 2.0 OTG Controller
cv_5v4
2016.10.28
17
16
1
0
chhlt
xfercomp
dmsk
lmsk
RW
RW 0x0
0x0
Reset
RW
0x0
RW
0x0
RW
0x0
RW
0x0
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