Altera cyclone V Technical Reference page 2302

Hard processor system

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This register indicates the status of a channel with respect to USB- and AHB-related events. The

application must read this register when the Host Channels Interrupt bit of the Core Interrupt register

(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All

Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt

HAINT and GINTSTS registers.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

Altera Corporation

This field is the port number of the recipient transac‐

tiontranslator.

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

Base Address

USB 2.0 OTG Controller

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