Altera cyclone V Technical Reference page 2221

Hard processor system

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ptxqspcavail

ptxfspcavail

When a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the

application using the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt). There

is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when

the application sets and clears bits in the corresponding Host Channel-n Interrupt register.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

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Indicates the number of free locations available to be

written in the Periodic Transmit Request Queue. This

queue holds both IN and OUT requests. Others:

Indicates the number of free locations available to be

written to in the Periodic TxFIFO. Values are in terms

of 32-bit words 16h0: Periodic TxFIFO is full 16h1: 1

word available 16h2: 2 words available 16hn: n words

available where n is 0 to 8192

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

Periodic Transmit Request Queue is full

1 location available

2 location available

3 location available

4 location available

5 location available

6 location available

7 location available

8 location available

Base Address

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