Altera cyclone V Technical Reference page 2523

cv_5v4
2016.10.28
Bit
0
xfercompl
dieptsiz1
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
Module Instance
usb0
usb1
Offset:
0x930
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved mc
RW 0x0
15 14
USB 2.0 OTG Controller
Send Feedback
Name
Applies to IN and OUT endpoints. When Scatter/
Gather DMA mode is enabled - for IN endpoint this
field indicates that the requested data from the
descriptor is moved from external system memory to
internal FIFO. - for OUT endpoint this field indicates
that the requested data from the internal FIFO is
moved to external system memory. This interrupt is
generated only when the corresponding endpoint
descriptor is closed, and the IOC bit for the
corresponding descriptor is Set. When Scatter/Gather
DMA mode is disabled, this field indicates that the
programmed transfer is complete on the AHB as well
as on the USB, for this endpoint.
Value
0x0
0x1
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Description
Description
No Interrupt
Transfer Completed Interrupt
Base Address
Bit Fields
25 24 23 22
PktCnt
RW 0x0
9 8 7 6
xfersize
RW 0x0
dieptsiz1
Access
Register Address
0xFFB00930
0xFFB40930
21 20 19 18
5 4 3 2
18-433
Reset
RO 0x0
17 16
xfersize
RW 0x0
1 0
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