Altera cyclone V Technical Reference page 2510

Hard processor system
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18-420
diepdma0
31
30
15
14
dieptsiz0 Fields
Bit
20:19
pktcnt
6:0
xfersize
diepdma0
DMA Addressing.
Module Instance
usb0
usb1
Offset:
0x914
Access:
RW
Altera Corporation
29
28
27
26
Reserved
13
12
11
10
Reserved
Name
Indicates the total number of USB packets that
constitute the Transfer Size amount of data for
endpoint 0. This field is decremented every time a
packet (maximum size or short packet) is read from
the TxFIFO.
Indicates the transfer size in bytes for endpoint 0. The
core interrupts the application only after it has
exhausted the transfer size amount of data. The
transfer size can be Set to the maximum packet size of
the endpoint, to be interrupted at the end of each
packet. The core decrements this field every time a
packet from the external memory is written to the
TxFIFO.
Bit Fields
25
24
23
22
9
8
7
6
Description
Base Address
0xFFB00000
0xFFB40000
21
20
19
18
pktcnt
RW 0x0
5
4
3
2
xfersize
RW 0x0
Access
Register Address
0xFFB00914
0xFFB40914
USB 2.0 OTG Controller
cv_5v4
2016.10.28
17
16
Reserved
1
0
Reset
RW
0x0
RW
0x0
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