Altera cyclone V Technical Reference page 2189

Hard processor system
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cv_5v4
2016.10.28
Bit
4
partialpwrdn
3:0
numdevperioeps
gdfifocfg
Specifies whether Dedicated Transmit FIFOs should be enabled in device mode.
Module Instance
usb0
usb1
Offset:
0x5C
Access:
RW
31
30
15
14
gdfifocfg Fields
Bit
31:16
epinfobaseaddr
15:0
gdfifocfg
USB 2.0 OTG Controller
Send Feedback
Name
Specifies whether to enable power optimization.
Value
0x0
The maximum number of device IN operations is 16
active at any time including endpoint 0, which is
always present. This parameter determines the
number of device mode Tx FIFOs to be instantiated.
0xFFB00000
0xFFB40000
29
28
27
26
13
12
11
10
Name
This field provides the start address of the EP info
controller.
This field is for dynamic programming of the DFIFO
Size. This value takes effect only when the application
programs a non zero value to this register. The otg
core does not have any corrective logic if the FIFO
sizes are programmed incorrectly.
Description
Description
Partial Power Down disabled
Base Address
Bit Fields
25
24
23
22
epinfobaseaddr
RW 0x1F80
9
8
7
6
gdfifocfg
RW 0x2000
Description
gdfifocfg
Access
Register Address
0xFFB0005C
0xFFB4005C
21
20
19
18
5
4
3
2
Access
18-99
Reset
RO
0x0
RO
0x0
17
16
1
0
Reset
RW
0x1F80
RW
0x2000
Altera Corporation

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