Altera cyclone V Technical Reference page 2185

Hard processor system
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cv_5v4
2016.10.28
Module Instance
usb0
usb1
Offset:
0x50
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
dma
dma_
confi
RO 0x1
gurat
ion
RO
0x1
15
14
phydatawidth
RO 0x0
ghwcfg4 Fields
Bit
31
dma
30
dma_configuration
USB 2.0 OTG Controller
Send Feedback
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
ineps
RO 0xF
13
12
11
10
Reserved
Name
Enable descriptor based scatter/gather DMA. When
enabled, DMA operations will be serviced with
descriptor based scatter/gather DMA
Value
0x1
Selects bewteen scatter and nonscatter configuration
Value
0x0
0x1
Base Address
Bit Fields
25
24
23
22
dedfi
sesse
bvali
avali
fomod
ndflt
dfltr
dfltr
e
r
RO
RO
RO
RO
0x0
0x0
0x1
0x0
9
8
7
6
hiber
natio
n
RO
0x0
Description
Description
Dynamic configuration
Description
Non-Scatter/Gather DMA configuration
Scatter/Gather DMA configuration
ghwcfg4
Register Address
0xFFB00050
0xFFB40050
21
20
19
18
vbusv
iddgf
numctleps
alidf
ltr
ltr
RO
RO
0x0
0x0
5
4
3
2
ahbfr
parti
numdevperioeps
eq
alpwr
dn
RO
0x1
RO
0x0
Access
18-95
17
16
RO 0xF
1
0
RO 0x0
Reset
RO
0x1
RO
0x1
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