Altera cyclone V Technical Reference page 2325

cv_5v4
2016.10.28
hcdmab6
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
Module Instance
usb0
usb1
Offset:
0x5D8
Access:
RW
31 30
15 14
hcdmab6 Fields
Bit
31:0
hcdmab6
hcchar7
Host Channel 7 Characteristics Register
Module Instance
usb0
usb1
USB 2.0 OTG Controller
Send Feedback
0xFFB00000
0xFFB40000
29 28 27 26
13 12 11 10
Name
These registers are present only in case of Scatter/
Gather DMA. These registers are implemented in
RAM instead of flop-based implementation. Holds
the current buffer address. This register is updated as
and when the data transfer for the corresponding end
point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is
reserved.
0xFFB00000
0xFFB40000
Base Address
Bit Fields
25 24 23 22
hcdmab6
RW 0x0
9 8 7 6
hcdmab6
RW 0x0
Description
Base Address
hcdmab6
Register Address
0xFFB005D8
0xFFB405D8
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB005E0
0xFFB405E0
18-235
17 16
1 0
Reset
RW 0x0
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