Altera cyclone V Technical Reference page 2498

18-408
diepempmsk
Bit
0
nonisothren
diepempmsk
This register is used to control the IN endpoint FIFO empty interrupt generation (DIEPINTn.TxfEmp).
Module Instance
usb0
usb1
Offset:
0x834
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
ineptxfe inept inept
mpmsk15 xfemp xfemp
msk14 msk13
RW 0x0
RW
0x0
diepempmsk Fields
Bit
15
ineptxfempmsk15
Altera Corporation
Name
When this bit is Set, the core enables thresholding for
Non Isochronous IN endpoints.
Value
0x0
0x1
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
inept inept inept
xfemp xfemp xfemp
msk12 msk11 msk10
RW RW RW RW
0x0 0x0 0x0 0x0
Name
This bit acts as mask bits for DIEPINT15.
Value
0x0
0x1
Description
Description
No thresholding
Enable thresholding
Base Address
0xFFB00000
0xFFB40000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
inept inept inept inept
xfemp xfemp xfemp xfemp
msk9 msk8 msk7 msk6
RW RW RW RW
0x0 0x0 0x0 0x0
Description
Description
Mask End point 15 interrupt
No mask
Register Address
0xFFB00834
0xFFB40834
21 20 19 18
5 4 3 2
inept inept inept inept
xfemp xfemp xfemp xfemp
msk5 msk4 msk3 msk2
RW RW RW RW
0x0 0x0 0x0 0x0
USB 2.0 OTG Controller
cv_5v4
2016.10.28
Access Reset
RW 0x0
17 16
1 0
inept ineptxfe
xfemp mpmsk0
msk1
RW 0x0
RW
0x0
Access Reset
RW 0x0
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