Altera cyclone V Technical Reference page 2454

18-364
Device Mode Registers Register Descriptions
dieptsiz2
on page 18-447
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
diepdma2
DMA Addressing.
DTXFSTS2
This register contains the free space information for the Device IN endpoint TxFIFO.
diepdmab2
DMA Buffer Address.
diepctl3
on page 18-451
Endpoint_number: 3
diepint3
on page 18-457
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
dieptsiz3
on page 18-461
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
diepdma3
DMA Addressing.
dtxfsts3
on page 18-463
This register contains the free space information for the Device IN endpoint TxFIFO.
diepdmab3
DMA Buffer Address.
diepctl4 on page 18-465
Endpoint_number: 4
diepint4
on page 18-471
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
Altera Corporation
on page 18-448
on page 18-449
on page 18-450
on page 18-462
on page 18-464
cv_5v4
2016.10.28
USB 2.0 OTG Controller
Send Feedback