Altera cyclone V Technical Reference page 2182

18-92
ghwcfg3
Bit
4:3
otgarch
2:0
otgmode
ghwcfg3
This register contains the configuration options.
Module Instance
usb0
usb1
Offset:
0x4C
Access:
RO
31 30
15 14
lpmmode bcsup hsicm
port
RO 0x0
RO
0x0
Altera Corporation
Name
DMA Architecture.
0x2
HNP- and SRP-Capable OTG (Device and Host).
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
29 28 27 26
13 12 11 10
adpsu rstty optfe
ode pport pe ature
RO RO RO RO
0x0 0x0 0x0 0x0
Description
Value
Internal DMA
Description
HNP- and SRP-Capable OTG (Host & Device
SRP-Capable OTG (Host & Device)
Non-HNP and Non-SRP Capable OTG (Host
& Device)
SRP-Capable Device
Non-OTG Device
SRP-Capable Host
Non-OTG Host
Base Address
0xFFB00000
0xFFB40000
Bit Fields
25 24 23 22
dfifodepth
RO 0x1F80
9 8 7 6
vndct i2cin otgen pktsizewidth
lsupt tsel
RO
RO RO 0x1
0x1 0x0
Description
Register Address
0xFFB0004C
0xFFB4004C
21 20 19
5 4 3
RO 0x6
cv_5v4
2016.10.28
Access Reset
RO 0x2
RO 0x0
18 17 16
2 1 0
xfersizewidth
RO 0x8
USB 2.0 OTG Controller
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