Altera cyclone V Technical Reference page 2155

Hard processor system

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USB 2.0 OTG Controller

Send Feedback

Mode:Host only. The core sets this bit to indicate a

change in port status of one of the otg core ports in

Host mode. The application must read the Host Port

Control and Status (HPRT) register to determine the

exact event that caused this interrupt. The application

must clear the appropriate status bit in the Host PC

Control and Status register to clear this bit.

Mode: Device only. In Device mode, this interrupt is

asserted when a reset is detected on the USB in partial

power-down mode when the device is in Suspend. In

Host mode, this interrupt is not asserted.

Host Port Interrupt

Reset detected Interrup

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