Altera cyclone V Technical Reference page 2298

Hard processor system

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When the Split Enable bit of the Host Channel-n Split

Control register (HCSPLTn.SpltEna) is reset (0), this

field indicates to the host the number of transactions

that must be executed per microframe for this periodic

endpoint. for non periodic transfers, this field is used

only in DMA mode, and specifies the number packets

to be fetched for this channel before the internal DMA

engine changes arbitration. 0x0: Reserved This field

yields undefined results. 0x1: transaction 0x2: 2

transactions to be issued for this endpoint permicro‐

frame 0x3: 3 transactions to be issued for this endpoint

permicroframeWhen HCSPLTn.SpltEna is Set (1), this

field indicates thenumber of immediate retries to be

performed for a periodic splittransactions on transac‐

tion errors. This field must be Set to atleast 1.

Indicates the transfer type selected.

Reserved This field yields undefined results

1 transaction

2 transactions to be issued for this endpoint per

3 transactions to be issued for this endpoint per

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