Altera cyclone V Technical Reference page 2149

cv_5v4
2016.10.28
Bit
10:6
txfnum
5
txfflsh
USB 2.0 OTG Controller
Send Feedback
Name
Mode:Host and Device. This is the FIFO number that
must be flushed using the TxFIFO Flush bit. This field
must not be changed until the core clears the TxFIFO
Flush bit.
Value
0x0
0x1
0x2
0xf
0x10 Flush all the transmit FIFOs in device or host
Mode:Host and Device. This bit selectively flushes a
single or all transmit FIFOs, but cannot do so If the
core is in the midst of a transaction. The application
must write this bit only after checking that the core is
neither writing to the TxFIFO nor reading from the
TxFIFO. Verify using these registers: ReadNAK
Effective Interrupt ensures the core is notreading
from the FIFO WriteGRSTCTL.AHBIdle ensures the
core is not writinganything to the FIFO. Flushing is
normally recommended when FIFOs are reconfigured
or when switching between Shared FIFO and
Dedicated Transmit FIFO operation. FIFO flushing is
also recommended during device endpoint disable.
The application must wait until the core clears this bit
before performing any operations. This bit takes eight
clocks to clear, using the slower clock of phy_clk or
hclk.
Value
0x0
0x1
Description
Description
- Non-periodic TxFIFO flush in Host mode -
Non-periodic TxFIFO flush in device mode
when in shared FIFO operation
- Periodic TxFIFO flush in Host mode -
Periodic TxFIFO 1 flush in Device mode
when in sharedFIFO operation
- Periodic TxFIFO 2 flush in Device mode
when in sharedFIFO operation- TXFIFO 2
flush in device mode when in dedicated FIFO
mode
- Periodic TxFIFO 15 flush in Device mode
when in shared FIFO operation - TXFIFO 15
flush in device mode when in dedicated FIFO
mode
mode.
Description
No Flush
selectively flushes a single or all transmit
FIFOs
18-59
grstctl
Access Reset
RW 0x0
RO 0x0
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