Altera cyclone V Technical Reference page 2504

Hard processor system

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This register indicates the status of an endpoint with respect to USB- and AHB-related events. The

application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of

the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the

application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to

get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the

appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.

Module Instance

Altera Corporation

When this bit is Set, either by the application or core,

the core stops transmitting data, even If there is data

available in the TxFIFO. Irrespective of this bit's

setting, the core always responds to SETUP data

packets with an ACK handshake.

This bit is always SET to 1, indicating that control

endpoint 0 is always active in all configurations and

Applies to IN and OUT endpoints.The application

must program this field with the maximum packet

size for the current logical endpoint.

The core is transmitting non-NAK

handshakes based on the FIFO status

The core is transmitting NAK handshakes on

this endpoint

Control endpoint is always active

Base Address

USB 2.0 OTG Controller

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