Altera cyclone V Technical Reference page 2452

cv_5v4
18-362
Device Mode Registers Register Descriptions
2016.10.28
dsts
on page 18-386
This register indicates the status of the core with respect to USB-related events. It must be read on
interrupts from Device All Interrupts (DAINT) register.
diepmsk
on page 18-388
This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers for all endpoints
to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn
register can be masked by writing to the corresponding bit in this register. Status bits are masked by
default.
doepmsk
on page 18-390
This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers for all
endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in
the DOEPINTn register can be masked by writing into the corresponding bit in this register. Status bits are
masked by default
daint
on page 18-392
When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the
application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the
Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). There is one interrupt bit per
endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. for a bidirectional
endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared
when the application sets and clears bits in the corresponding Device Endpoint-n Interrupt register
(DIEPINTn/DOEPINTn).
daintmsk
on page 18-398
The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to
interrupt the application when an event occurs on a device endpoint. However, the Device All Endpoints
Interrupt (DAINT) register bit corresponding to that interrupt is still set.
dvbusdis
on page 18-403
This register specifies the VBUS discharge time after VBUS pulsing during SRP.
dvbuspulse
on page 18-404
This register specifies the VBUS pulsing time during SRP.
dthrctl on page 18-405
Thresholding is not supported in Slave mode and so this register must not be programmed in Slave mode.
for threshold support, the AHB must be run at 60 MHz or higher.
diepempmsk on page 18-408
This register is used to control the IN endpoint FIFO empty interrupt generation (DIEPINTn.TxfEmp).
diepctl0
on page 18-411
This register covers Device Control IN Endpoint 0.
diepint0
on page 18-414
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
USB 2.0 OTG Controller
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