Altera cyclone V Technical Reference page 2488

18-398
daintmsk
Bit
1
inepint1
0
inepint0
daintmsk
The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to
interrupt the application when an event occurs on a device endpoint. However, the Device All Endpoints
Interrupt (DAINT) register bit corresponding to that interrupt is still set.
Module Instance
usb0
usb1
Offset:
0x81C
Access:
RW
31 30
outepmsk OutEP outep
15 Msk14 msk13
RW 0x0 RW
0x0
15 14
InEpMsk1 inepm InEpM
5 sk14 sk13
RW 0x0 RW
0x0
Altera Corporation
Name
Value
0x0
0x1
Value
0x0
0x1
29 28 27 26
outep outep outep
msk12 msk11 msk10
RW RW RW RW
0x0 0x0 0x0 0x0
13 12 11 10
inepm inepm inepm
sk12 sk11 sk10
RW RW RW RW
0x0 0x0 0x0 0x0
Description
Description
No Interrupt
IN Endpoint 1 Interrupt
Description
No Interrupt
IN Endpoint 0 Interrupt
Base Address
0xFFB00000
0xFFB40000
Bit Fields
25 24 23 22
outep outep outep outep
msk9 msk8 msk7 msk6
RW RW RW RW
0x0 0x0 0x0 0x0
9 8 7 6
inepm inepm inepm inepm
sk9 sk8 sk7 sk6
RW RW RW RW
0x0 0x0 0x0 0x0
Register Address
0xFFB0081C
0xFFB4081C
21 20 19 18
outep outep OutEP outep
msk5 msk4 Msk3 msk2
RW RW RW RW
0x0 0x0 0x0 0x0
5 4 3 2
inepm inepm inepm inepm
sk5 sk4 sk3 sk2
RW RW RW RW
0x0 0x0 0x0 0x0
USB 2.0 OTG Controller
cv_5v4
2016.10.28
Access Reset
RO 0x0
RO 0x0
17 16
outep outepmsk
msk1 0
RW RW 0x0
0x0
1 0
inepm inepmsk0
sk1
RW 0x0
RW
0x0
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