Altera cyclone V Technical Reference page 2139

cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
gahbcfg Fields
Bit
22
notialldmawrit
USB 2.0 OTG Controller
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
Reserved
Name
This bit is programmed to enable the System DMA
Done functionality for all the DMA write Transac‐
tions corresponding to the Channel/​Endpoint. This
bit is valid only when GAHBCFG.RemMemSupp is
set to 1.
Value
0x1
0x0
Bit Fields
25 24 23 22
notia
lldma
writ
RW
0x0
9 8 7 6
ptxfe nptxf Reser
mplvl emplv ved
l
RW
0x0 RW
0x0
Description
Description
HSOTG core asserts int_dma_req for all the
DMA write transactions on the AHB
interface along with int_dma_done, chep_
last_transact and chep_number signal
informations. The core waits for sys_dma_
done signal for all the DMA write transac‐
tions in order to complete the transfer of a
particular Channel/Endpoint
HSOTG core asserts int_dma_req signal only
for the last transaction of DMA write transfer
corresponding to a particular Channel/
Endpoint. Similarly, the core waits for sys_
dma_done signal only for that transaction of
DMA write to complete the transfer of a
particular Channel/Endpoint
gahbcfg
21 20 19 18
remme Reserved
msupp
RW
0x0
5 4 3 2
dmaen hbstlen
RW RW 0x0
0x0
Access
18-49
17 16
1 0
glblintr
msk
RW 0x0
Reset
RW 0x0
Altera Corporation