Altera cyclone V Technical Reference page 2242

18-152
hcchar1
Offset:
0x518
Access:
RW
31 30
15 14
hcdmab0 Fields
Bit
31:0
hcdmab0
hcchar1
Host Channel 1 Characteristics Register
Module Instance
usb0
usb1
Offset:
0x520
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
29 28 27 26
13 12 11 10
Name
These registers are present only in case of Scatter/
Gather DMA. These registers are implemented in
RAM instead of flop-based implementation. Holds
the current buffer address. This register is updated as
and when the data transfer for the corresponding end
point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is
reserved.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
hcdmab0
RW 0x0
9 8 7 6
hcdmab0
RW 0x0
Description
Base Address
0xFFB00000
0xFFB40000
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB00520
0xFFB40520
USB 2.0 OTG Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x0
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