Altera cyclone V Technical Reference page 2183

Hard processor system
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cv_5v4
2016.10.28
ghwcfg3 Fields
Bit
31:16
dfifodepth
15
lpmmode
14
bcsupport
13
hsicmode
12
adpsupport
11
rsttype
10
optfeature
9
vndctlsupt
USB 2.0 OTG Controller
Send Feedback
Name
DFIFO Depth. This value is in terms of 35-bit words.
Minimum value is 32 Maximum value is 8192
LPM Mode Enabled/Disabled.
Value
0x0
Battery Charger Support.
Value
0x0
Supports HSIC and Non-HSIC Modes.
Value
0x0
ADP logic support.
Value
0x1
Defines what reset type is used in the core.
Value
0x0
User ID register, GPIO interface ports, and SOF
toggle and counter ports were removed.
Value
0x0
ULPI PHY internal registers can be accessed by
software using register reads/writes to otg
Value
0x1
Description
Description
LPM disabled
Description
No Battery Charger Support
Description
Non-HSIC-capable
Description
ADP logic is present along with HSOTG
controller
Description
Asynchronous reset is used in the core
Description
No Optional features
Description
Vendor Control Interface is not available on
the
18-93
ghwcfg3
Access
Reset
RO
0x1F80
RO
0x0
RO
0x0
RO
0x0
RO
0x0
RO
0x0
RO
0x0
RO
0x1
Altera Corporation

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