Altera cyclone V Technical Reference page 2127

cv_5v4
2016.10.28
USB Direct Access FIFO RAM Address Map
Name
Direct_FIFO
Global Registers Register Descriptions
These registers are available in both Host and Device modes, and do not need to be reprogrammed when
switching between these modes.
Offset:
0x0
gotgctl
on page 18-40
The OTG Control and Status register controls the behavior and reflects the status of the OTG function.
gotgint
on page 18-46
The application reads this register whenever there is an OTG interrupt and clears the bits in this register to
clear the OTG interrupt.
gahbcfg
on page 18-48
This register can be used to configure the core after power-on or a change in mode. This register mainly
contains AHB system-related configuration parameters. Do not change this register after the initial
programming. The application must program this register before starting any transactions on either the
AHB or the USB.
gusbcfg
on page 18-52
This register can be used to configure the core after power-on or a changing to Host mode or Device
mode. It contains USB and USB-PHY related configuration parameters. The application must program
this register before starting any transactions on either the AHB or the USB. Do not make changes to this
register after the initial programming.
grstctl
on page 18-57
The application uses this register to reset various hardware features inside the core
gintsts on page 18-61
This register interrupts the application for system-level events in the current mode (Device mode or Host
mode). Some of the bits in this register are valid only in Host mode, while others are valid in Device mode
only. This register also indicates the current mode. To clear the interrupt status bits of type R_SS_WC, the
application must write 1 into the bit. The FIFO status interrupts are read only; once software reads from or
writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically.
The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to
avoid any interrupts generated prior to initialization.
gintmsk on page 18-71
This register works with the Interrupt Register (GINTSTS) to interrupt the application. When an interrupt
bit is masked, the interrupt associated with that bit is not generated. However, the GINTSTS register bit
corresponding to that interrupt is still set.
USB 2.0 OTG Controller
Send Feedback
Description
This address space is
allocated for directly
accessing the data FIFO
for debugging
purposes.
Global Registers Register Descriptions
Start Address Offset
0x20000
18-37
End Address Offset
0x3FFFF
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