Altera cyclone V Technical Reference page 2204

18-114
Host Mode Registers Register Descriptions
hflbaddr
on page 18-133
This Register is valid only for Host mode Scatter-Gather DMA. Starting address of the Frame list. This
register is used only for Isochronous and Interrupt Channels.
hprt
on page 18-134
This register is available only in Host mode. Currently, the OTG Host supports only one port. A single
register holds USB port-related information such as USB reset, enable, suspend, resume, connect status,
and test mode for each port.The R_SS_WC bits in this register can trigger an interrupt to the application
through the Host Port Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). On a Port Interrupt,
the application must read this register and clear the bit that caused the interrupt. for the R_SS_WC bits,
the application must write a 1 to the bit to clear the interrupt
hcchar0
on page 18-138
Channel_number: 0.
hcsplt0 on page 18-141
Channel_number 0
hcint0
on page 18-143
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
hcintmsk0
This register reflects the mask for each channel status described in the previous section.
hctsiz0
on page 18-149
Buffer DMA Mode
hcdma0 on page 18-150
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
hcdmab0
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcchar1
on page 18-152
Host Channel 1 Characteristics Register
hcsplt1 on page 18-155
Channel_number 1
hcint1
on page 18-157
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
Altera Corporation
on page 18-147
on page 18-151
cv_5v4
2016.10.28
USB 2.0 OTG Controller
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