Altera cyclone V Technical Reference page 2457

cv_5v4
2016.10.28
dieptsiz8
on page 18-531
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
diepdma8
DMA Addressing.
dtxfsts8
on page 18-533
This register contains the free space information for the Device IN endpoint TxFIFO.
diepdmab8
DMA Buffer Address.
diepctl9 on page 18-535
Endpoint_number: 9
diepint9
on page 18-541
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
dieptsiz9 on page 18-545
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
diepdma9
DMA Addressing.
dtxfsts9
on page 18-547
This register contains the free space information for the Device IN endpoint TxFIFO.
diepdmab9
DMA Buffer Address.
diepctl10
on page 18-549
Endpoint_number: 10
diepint10
on page 18-555
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
USB 2.0 OTG Controller
Send Feedback
on page 18-532
on page 18-534
on page 18-546
on page 18-548
Device Mode Registers Register Descriptions
18-367
Altera Corporation