Altera cyclone V Technical Reference page 2311

cv_5v4
2016.10.28
Offset:
0x5B8
Access:
RW
31 30
15 14
hcdmab5 Fields
Bit
31:0
hcdmab5
hcchar6
Host Channel 6 Characteristics Register
Module Instance
usb0
usb1
Offset:
0x5C0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
USB 2.0 OTG Controller
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29 28 27 26
13 12 11 10
Name
These registers are present only in case of Scatter/
Gather DMA. These registers are implemented in
RAM instead of flop-based implementation. Holds
the current buffer address. This register is updated as
and when the data transfer for the corresponding end
point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is
reserved.
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
hcdmab5
RW 0x0
9 8 7 6
hcdmab5
RW 0x0
Description
Base Address
hcchar6
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB005C0
0xFFB405C0
18-221
17 16
1 0
Reset
RW 0x0
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