Altera cyclone V Technical Reference page 2509

Hard processor system

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The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using

Endpoint Enable bit of the Device Control Endpoint 0 Control registers (DIEPCTL0.EPEna/

DOEPCTL0.EPEna), the core modifies this register. The application can only read this register once the

core has cleared the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 1 to 15. When

Scatter/Gather DMA mode is enabled, this register must not be programmed by the application. If the

application reads this register when Scatter/Gather DMA mode is enabled, the core returns all zeros.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

USB 2.0 OTG Controller

Send Feedback

Applies to IN and OUT endpoints. When Scatter/

Gather DMA mode is enabled - for IN endpoint this

field indicates that the requested data from the

descriptor is moved from external system memory to

internal FIFO. - for OUT endpoint this field indicates

that the requested data from the internal FIFO is

moved to external system memory. This interrupt is

generated only when the corresponding endpoint

descriptor is closed, and the IOC bit for the

corresponding descriptor is Set. When Scatter/Gather

DMA mode is disabled, this field indicates that the

programmed transfer is complete on the AHB as well

as on the USB, for this endpoint.

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

No Interrupt

Transfer Completed Interrupt

Base Address

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