Altera cyclone V Technical Reference page 2501

cv_5v4
2016.10.28
Bit
2
ineptxfempmsk2
1
ineptxfempmsk1
0
ineptxfempmsk0
diepctl0
This register covers Device Control IN Endpoint 0.
Module Instance
usb0
usb1
Offset:
0x900
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
USB 2.0 OTG Controller
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Name
This bit acts as mask bits for DIEPINT2.
Value
0x0
0x1
This bit acts as mask bits for DIEPINT1.
Value
0x0
0x1
This bit acts as mask bits for DIEPINT0.
Value
0x0
0x1
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
Mask End point 2 interrupt
No mask
Description
Mask End point 1 interrupt
No mask
Description
Mask End point 0 interrupt
No mask
Base Address
0xFFB00900
0xFFB40900
18-411
diepctl0
Access Reset
RW 0x0
RW 0x0
RW 0x0
Register Address
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