Altera cyclone V Technical Reference page 2154

Hard processor system

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ConIDStsChng

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Mode:Host and Device. The core sets this bit when

there is a change in connector ID status. This bit can

be set only by the core and the application should

write 1 to clear it.

Mode:Host only. This interrupt is asserted when the

Periodic Transmit FIFO is either half or completely

empty and there is space for at least one entry to be

written in the Periodic Request Queue. The half or

completely empty status is determined by the Periodic

TxFIFO Empty Level bit in the Core AHB Configura‐

tion register (GAHBCFG.PTxFEmpLvl).

Mode:Host only. The core sets this bit to indicate that

an interrupt is pending on one of the channels of the

core (in Host mode). The application must read the

Host All Channels Interrupt (HAINT) register to

determine the exact number of the channel on which

the interrupt occurred, and Then read the

corresponding Host Channel-n Interrupt (HCINTn)

The application must clear the appropriate status bit

in the HCINTn register to clear this bit.

Connector ID Status Change

Periodic TxFIFO Empty

Host Channels Interrupt

USB 2.0 OTG Controller

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