Altera cyclone V Technical Reference page 2209

cv_5v4
2016.10.28
hcintmsk8
This register reflects the mask for each channel status described in the previous section.
hctsiz8 on page 18-260
Buffer DMA Mode
hcdma8
on page 18-261
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
hcdmab8
on page 18-263
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcchar9
on page 18-263
Host Channel 9 Characteristics Register
hcsplt9 on page 18-266
Channel_number 9
hcint9
on page 18-268
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
hcintmsk9
This register reflects the mask for each channel status described in the previous section.
hctsiz9
on page 18-274
Buffer DMA Mode
hcdma9 on page 18-275
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
hcdmab9
on page 18-277
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcchar10
on page 18-277
Host Channel 1 Characteristics Register
hcsplt10 on page 18-280
Channel_number 1
USB 2.0 OTG Controller
Send Feedback
on page 18-258
on page 18-272
Host Mode Registers Register Descriptions
18-119
Altera Corporation