Altera cyclone V Technical Reference page 2203

cv_5v4
2016.10.28
31 30
Reserved
15 14
dieptxf15 Fields
Bit
29:16
inepntxfdep
15:0
inepntxfstaddr
Host Mode Registers Register Descriptions
These registers must be programmed every time the USB OTG Controller changes to Host mode.
Offset:
0x400
hcfg on page 18-123
Host Mode control. This register must be programmed every time the core changes to Host mode
hfir
on page 18-126
This register stores the frame interval information for the current speed to which the otg core has
enumerated
hfnum
on page 18-127
This register contains the free space information for the Periodic TxFIFO and the Periodic Transmit
Request Queue
hptxsts on page 18-128
This register contains the free space information for the Periodic TxFIFO and the Periodic Transmit
Request Queue.
haint
on page 18-131
When a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the
application using the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt). There
is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when
the application sets and clears bits in the corresponding Host Channel-n Interrupt register.
haintmsk on page 18-132
The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to
interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel,
up to a maximum of 16 bits.
USB 2.0 OTG Controller
Send Feedback
29 28 27 26
13 12 11 10
Name
This value is in terms of 32-bit words. Minimum value
is 16 Maximum value is 8192.
This field contains the memory start address for IN
endpoint Transmit FIFO 15.
Host Mode Registers Register Descriptions
Bit Fields
25 24 23 22
inepntxfdep
RW 0x2000
9 8 7 6
inepntxfstaddr
RW 0x0
Description
21 20 19 18
5 4 3 2
Access
RW
RW
18-113
17 16
1 0
Reset
0x2000
0x0
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