Altera cyclone V Technical Reference page 2246

Hard processor system
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18-156
hcsplt1
Offset:
0x524
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
spltena
RW 0x0
15
14
xactpos
RW 0x0
hcsplt1 Fields
Bit
31
spltena
16
compsplt
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
hubaddr
RW 0x0
Name
The application sets this field to indicate that this
channel is enabled to perform split transactions.
0x0
0x1
The application sets this field to request the OTG host
to perform a complete split transaction.
Value
0x0
0x1
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Description
Value
Description
Split not enabled
Split enabled
Description
No split transaction
Split transaction
21
20
19
18
5
4
3
2
prtaddr
RW 0x0
Access
USB 2.0 OTG Controller
cv_5v4
2016.10.28
17
16
compsplt
RW 0x0
1
0
Reset
RW
0x0
RW
0x0
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