Altera cyclone V Technical Reference page 2110
Hard processor system
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Also See for cyclone V:
- Device handbook (1077 pages) ,
- User manual (136 pages) ,
- Reference manual (66 pages)
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18-20
USB OTG Controller Module Registers Address Map
Register
haint
on page 18-131
haintmsk
on page 18-
132
hflbaddr
on page 18-
133
hprt
on page 18-134
hcchar0
on page 18-
138
hcsplt0
on page 18-
141
hcint0
on page 18-143
hcintmsk0
on page 18-
147
hctsiz0
on page 18-
149
hcdma0
on page 18-150
hcdmab0
on page 18-
151
hcchar1
on page 18-
152
hcsplt1
on page 18-
155
hcint1
on page 18-157
hcintmsk1
on page 18-
161
hctsiz1
on page 18-
163
hcdma1
on page 18-164
hcdmab1
on page 18-
166
hcchar2
on page 18-
166
hcsplt2
on page 18-
169
hcint2
on page 18-171
Altera Corporation
Offset
Width Acces
s
0x414
32
RO
0x418
32
RW
0x41C
32
RW
0x440
32
RW
0x500
32
RW
0x504
32
RW
0x508
32
RO
0x50C
32
RW
0x510
32
RW
0x514
32
RW
0x518
32
RW
0x520
32
RW
0x524
32
RW
0x528
32
RO
0x52C
32
RW
0x530
32
RW
0x534
32
RW
0x538
32
RW
0x540
32
RW
0x544
32
RW
0x548
32
RO
Reset Value
Host All Channels Interrupt
0x0
Register
Host All Channels Interrupt Mask
0x0
Register
Host Frame List Base Address
0x0
Register
Host Port Control and Status
0x0
Register
Host Channel 0 Characteristics
0x0
Register
Host Channel 0 Split Control
0x0
Register
Host Channel 0 Interrupt Register
0x0
Host Channel 0 Interrupt Mask
0x0
Register
Host Channel 0 Transfer Size
0x0
Register
Host Channel 0 DMA Address
0x0
Register
Host Channel 0 DMA Buffer
0x0
Address Register
Host Channel 1 Characteristics
0x0
Register
Host Channel 1 Split Control
0x0
Register
Host Channel 1 Interrupt Register
0x0
Host Channel 1 Interrupt Mask
0x0
Register
Host Channel 1 Transfer Size
0x0
Register
Host Channel 1 DMA Address
0x0
Register
Host Channel 1 DMA Buffer
0x0
Address Register
Host Channel 2 Characteristics
0x0
Register
Host Channel 2 Split Control
0x0
Register
Host Channel 2 Interrupt Register
0x0
cv_5v4
2016.10.28
Description
USB 2.0 OTG Controller
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