Altera cyclone V Technical Reference page 2160

Hard processor system

Hide thumbs Also See for cyclone V:

Table of Contents

Altera Corporation

Mode: Host and Device. Indicates that there is at least

one packet pending to be read from the RxFIFO.

Mode: Host and Device. In Host mode, the core sets

this bit to indicate that an SOF (FS), micro-SOF (HS),

or Keep-Alive (LS) is transmitted on the USB. The

application must write a 1 to this bit to clear the

interrupt. In Device mode, the core sets this bit to

indicate that an SOF token has been received on the

USB. The application can read the Device Status

interrupt is seen only when the core is operating at

either HS or FS. This bit can be set only by the core

and the application should write 1 to clear it. This

on reset. If the register bit reads 1 immediately after

power on reset it does not indicate that an SOF has

been sent (in case of host mode) or SOF has been

received (in case of device mode). The read value of

this interrupt is valid only after a valid connection

between host and device is established. If the bit is set

after power on reset the application can clear the bit.

Mode: Host and Device. The core sets this bit to

indicate an OTG protocol event. The application must

read the OTG Interrupt Status (GOTGINT) register

to determine the exact event that caused this

interrupt. The application must clear the appropriate

status bit in the GOTGINT register to clear this bit.

Rx Fifo Non Empty

Start of Frame

No Interrupt

OTG Interrupt

USB 2.0 OTG Controller

Send Feedback

Show Quick Links

Table of Contents