Altera cyclone V Technical Reference page 2161

Hard processor system

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This register works with the Interrupt Register (GINTSTS) to interrupt the application. When an interrupt

bit is masked, the interrupt associated with that bit is not generated. However, the GINTSTS register bit

corresponding to that interrupt is still set.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

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Mode: Host and Device. The core sets this bit when

the application is trying to access: -A Host mode

A Device mode register, when the core is operating in

Host mode. The register access is completed on the

AHB with an OKAYresponse, but is ignored by the

core internally and does not affect the operation of

the core. This bit can be set only by the core and the

application should write 1 to clearit

Mode: Host and Device. Indicates the current mode.

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

No Mode Mismatch Interrupt

Mode Mismatch Interrupt

Base Address

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