Altera cyclone V Technical Reference page 2478

18-388
diepmsk
Bit
0
suspsts
diepmsk
This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers for all endpoints
to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn
register can be masked by writing to the corresponding bit in this register. Status bits are masked by
default.
Module Instance
usb0
usb1
Offset:
0x810
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved nakms
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Name
In Device mode, this bit is Set as long as a Suspend
condition is detected on the USB. The core enters the
Suspended state when there is no activity on the phy_
line_state_i signal for an extended period of time. The
core comes out of the suspend: -When there is any
activity on the phy_line_state_i signal -When the
application writes to the Remote Wakeup Signaling
bit in the Device Control register
(DCTL.RmtWkUpSig).
0x0
0x1
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
k
RW
0x0
Description
Value Description
No suspend state
Suspend state
Base Address
0xFFB00000
0xFFB40000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
bnain txfif Reser inepn
intrm oundr ved akeff
sk nmsk msk
RW RW RW
0x0 0x0 0x0
Register Address
0xFFB00810
0xFFB40810
21 20 19 18
5 4 3 2
intkn intkn timeo ahber
epmis txfem utmsk rmsk
msk pmsk
RW RW
RW RW 0x0 0x0
0x0 0x0
USB 2.0 OTG Controller
cv_5v4
2016.10.28
Access Reset
RO 0x0
17 16
1 0
epdis xfercomp
bldms lmsk
k
RW 0x0
RW
0x0
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