Altera cyclone V Technical Reference page 2208

18-118
Host Mode Registers Register Descriptions
hcdma6
on page 18-233
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
hcdmab6
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcchar7
on page 18-235
Host Channel 7 Characteristics Register
hcsplt7
on page 18-238
Channel_number 7
hcint7 on page 18-240
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
hcintmsk7
This register reflects the mask for each channel status described in the previous section.
hctsiz7
on page 18-246
Buffer DMA Mode
hcdma7
on page 18-247
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
hcdmab7
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcchar8
on page 18-249
Host Channel 8 Characteristics Register
hcsplt8
on page 18-252
Channel_number 8
hcint8 on page 18-254
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
Altera Corporation
on page 18-235
on page 18-244
on page 18-249
cv_5v4
2016.10.28
USB 2.0 OTG Controller
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