Altera cyclone V Technical Reference page 2190

18-100
hptxfsiz
hptxfsiz
This register holds the size and the memory start address of the Periodic TxFIFO
Module Instance
usb0
usb1
Offset:
0x100
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
Reserved
hptxfsiz Fields
Bit
29:16
ptxfsize
14:0
ptxfstaddr
dieptxf1
This register holds the size and memory start address of IN endpoint TxFIFOs implemented in Device
mode. Each FIFO holds the data for one IN endpoint. This register is repeated for each instantiated IN
endpoint FIFO. For IN endpoint FIFO 0 use GNPTXFSIZ register for programming the size and memory
start address.
Module Instance
usb0
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This value is in terms of 32-bit words. Minimum value
is 16 Maximum value is 1024 The power-on reset
value of this register is specified as the 1024.
The power-on reset value of this register is the sum of
the Largest Rx Data FIFO Depth and Largest Non-
periodic Tx Data FIFO. Programmed values must not
exceed the power-on value
Base Address
0xFFB00000
0xFFB40000
Bit Fields
25 24 23 22
ptxfsize
RW 0x2000
9 8 7 6
ptxfstaddr
RW 0x4000
Description
Base Address
0xFFB00000
Register Address
0xFFB00100
0xFFB40100
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB00104
USB 2.0 OTG Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x2000
RW 0x4000
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