Altera cyclone V Technical Reference page 2129

cv_5v4
2016.10.28
ghwcfg4
on page 18-94
This register contains the configuration options.
gdfifocfg on page 18-99
Specifies whether Dedicated Transmit FIFOs should be enabled in device mode.
hptxfsiz
on page 18-100
This register holds the size and the memory start address of the Periodic TxFIFO
dieptxf1 on page 18-100
This register holds the size and memory start address of IN endpoint TxFIFOs implemented in Device
mode. Each FIFO holds the data for one IN endpoint. This register is repeated for each instantiated IN
endpoint FIFO. For IN endpoint FIFO 0 use GNPTXFSIZ register for programming the size and memory
start address.
dieptxf2 on page 18-101
This register holds the size and memory start address of IN endpoint TxFIFOs implemented in Device
mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint
FIFO. For IN endpoint FIFO 0 use GNPTXFSIZ register for programming the size and memory start
address.
dieptxf3
on page 18-102
This register holds the size and memory start address of IN endpoint TxFIFOs implemented in Device
mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint
FIFO. For IN endpoint FIFO 0 use GNPTXFSIZ register for programming the size and memory start
address.
dieptxf4
on page 18-103
This register holds the size and memory start address of IN endpoint TxFIFOs implemented in Device
mode. Each FIFO holds the data for one IN endpoint. This register is repeated for each instantiated IN
endpoint FIFO. For IN endpoint FIFO 0 use GNPTXFSIZ register for programming the size and memory
start address.
dieptxf5
on page 18-104
This register holds the size and memory start address of IN endpoint TxFIFOs implemented in Device
mode. Each FIFO holds the data for one IN endpoint. This register is repeated for each instantiated IN
endpoint FIFO. For IN endpoint FIFO 0 use GNPTXFSIZ register for programming the size and memory
start address.
dieptxf6
on page 18-105
This register holds the size and memory start address of IN endpoint TxFIFOs implemented in Device
mode. Each FIFO holds the data for one IN endpoint. This register is repeated for each instantiated IN
endpoint FIFO. For IN endpoint FIFO 0 use GNPTXFSIZ register for programming the size and memory
start address.
dieptxf7
on page 18-105
This register holds the size and memory start address of IN endpoint TxFIFOs implemented in Device
mode. Each FIFO holds the data for one IN endpoint. This register is repeated for each instantiated IN
endpoint FIFO. For IN endpoint FIFO 0 use GNPTXFSIZ register for programming the size and memory
start address.
USB 2.0 OTG Controller
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Global Registers Register Descriptions
18-39
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