Altera cyclone V Technical Reference page 2207

cv_5v4
2016.10.28
hcdmab4
on page 18-205
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcchar5
on page 18-206
Channel_number: 5.
hcsplt5
on page 18-210
Channel_number 5
hcint5
on page 18-212
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
hcintmsk5
This register reflects the mask for each channel status described in the previous section.
hctsiz5
on page 18-218
Buffer DMA Mode
hcdma5 on page 18-219
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
hcdmab5 on page 18-220
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcchar6 on page 18-221
Host Channel 6 Characteristics Register
hcsplt6
on page 18-224
Channel_number 6
hcint6 on page 18-226
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
hcintmsk6
This register reflects the mask for each channel status described in the previous section.
hctsiz6 on page 18-232
Buffer DMA Mode
USB 2.0 OTG Controller
Send Feedback
on page 18-216
on page 18-230
Host Mode Registers Register Descriptions
18-117
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