Altera cyclone V Technical Reference page 2408

Hard processor system
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18-318
hcdma12
Module Instance
usb0
usb1
Offset:
0x694
Access:
RW
31
30
15
14
hcdma12 Fields
Bit
31:0
hcdma12
Altera Corporation
29
28
27
26
13
12
11
10
Name
Non-Isochronous: This field holds the start address of
the 512 bytes page. The first descriptor in the list
should be located in this address. The first descriptor
may be or may not be ready. The core starts
processing the list from the CTD value. This field
holds the address of the 2*(nTD+1) bytes of locations
in which the isochronous descriptors are present
where N is based on nTD as per Table below [31:N]
Base Address [N-1:3] Offset [2:0] 000 HS ISOC FS
ISOC nTD N nTD N 7 6 1 4 15 7 3 5 31 8 7 6 63 9 15 7
127 10 31 8 255 11 63 9 [N-1:3] (Isoc):[8:3] (Non
Isoc): Current Transfer Desc(CTD): Non Isochro‐
nous: This value is in terms of number of descriptors.
The values can be from 0 to 63. 0 - 1 descriptor. 63 -
64 descriptors. This field indicates the current
descriptor processed in the list. This field is updated
both by application and the core. for example, if the
application enables the channel after programming
CTD=5, then the core will start processing the 6th
descriptor. The address is obtained by adding a value
of (8bytes*5=) 40(decimal) to DMAAddr. Isochro‐
nous: CTD for isochronous is based on the current
frame/microframe value. Need to be set to zero by
application.
Base Address
0xFFB00000
0xFFB40000
Bit Fields
25
24
23
22
hcdma12
RW 0x0
9
8
7
6
hcdma12
RW 0x0
Description
Register Address
0xFFB00694
0xFFB40694
21
20
19
18
5
4
3
2
Access
USB 2.0 OTG Controller
cv_5v4
2016.10.28
17
16
1
0
Reset
RW
0x0
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