Altera cyclone V Technical Reference page 2418

Hard processor system
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18-328
hcintmsk13
Bit
2
ahberr
1
chhltd
0
xfercompl
hcintmsk13
This register reflects the mask for each channel status described in the previous section.
Module Instance
usb0
usb1
Offset:
0x6AC
Access:
RW
Altera Corporation
Name
This is generated only in Internal DMA mode when
there is an AHB error during AHB read/​write. The
application can read the corresponding channel's
DMA address register to get the error address.
Value
0x0
0x1
In non Scatter/Gather DMA mode, it indicates the
transfer completed abnormally either because of any
USB transaction error or in response to disable
request by the application or because of a completed
transfer. In Scatter/gather DMA mode, this indicates
that transfer completed due to any of the following .
EOL being set in descriptor . AHB error . Excessive
transaction errors . Babble . Stall
Value
0x0
0x1
Transfer completed normally without any errors. This
bit can be set only by the core and the application
should write 1 to clear it.
Value
0x0
0x1
0xFFB00000
0xFFB40000
Description
Description
No AHB error
AHB error during AHB read/write
Description
Channel not halted
Channel Halted
Description
No transfer
Transfer completed normally without any
errors
Base Address
Access
Register Address
0xFFB006AC
0xFFB406AC
USB 2.0 OTG Controller
cv_5v4
2016.10.28
Reset
RO
0x0
RO
0x0
RO
0x0
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